1. Field of Invention
The present invention relates to boundary scan circuitry and in particular the creation and use of the boundary scan circuitry to reduce power consumption and leakage problems during sleep mode.
2. Description of Related Art
Boundary scan is an architecture defined by IEEE Std. 1149.1 that is used for testing circuitry 1) between packaged integrated circuit chips and 2) to force test signals upon the core logic within an integrated circuit chip, both without the need to physically probe connections on a physical package, or printed circuit board. Boundary scan has proven very useful in determining shorts and opens that may exist in the wiring between semiconductor chips mounted on a board or similar package. Because the boundary scan circuitry is located at each I/O pin of an integrated circuit chip, boundary scan can also be useful in forcing logic signals on the internal core logic of the chip.
U.S. Pat. No. 7,167,991 B1 (Higashida) is directed to a method for reducing leakage current in an LSI chip using a scan path and a backup power region, where scan data from a main power region is saved into the backup power region. U.S. Pat. No. 6,671,860 B2 (Langford I I.) is directed to a structure and method for using an enhanced boundary scan register structure to permit flexible application of “stuck at fault” or normal operation at each I/O pad of an integrated circuit chip. In U.S. Pat. No. 6,658,632 B1 (Parulkar et al.) a design is directed to a high speed boundary scan cell for output pins, where location of conventional functional storage element and multiplex stages has been rearranged, which allows functional data to be latched into a storage element after multiplexing with boundary scan data. In U.S. Pat. No. 6,429,454 B2 (Hatada et al.) a method is directed to an implementation of a test using a boundary scan circuit synchronized with a cycle time defined by a normal operating clock signal.
U.S. Pat. No. 6,185,710 B1 (Barnhardt) is directed to circuitry containing a boundary scan cell that is connected to a second input and a control input to a slave latch of a master-slave combination so that the boundary scan cell can provide control signal and data to the slave latch. U.S. Pat. No. 6,108,807 (Ke) is directed to a method and apparatus to provide a hybrid pin control of output pins using a boundary scan architecture. U.S. Pat. No. 5,859,860 (Whetsel) is directed to a low overhead input and output boundary scan cells that include latchable input and output buffers from circuitry within which the boundary scan cells are provided. U.S. Pat. No. 5,491,666 (Sturges) is directed to a plurality of boundary scan cells, each associated with different portions of logic on an integrated circuit chip in which registers of the individual boundary scan circuits are chained together to create a series boundary scan chain to manipulate circuitry within the integrated circuit chip. U.S. Pat. No. 5,490,151 (Ferger et al.) is directed to a boundary scan cell to enable testing of an electronic circuit, wherein the boundary scan cell is connected in series with other boundary scan cells that are associated with other circuits.
In FIG. 1A of prior art is shown the basic configuration of the architecture for boundary scan used on semiconductor chips. A logic signal is received by an input pad circuit (IPC) 10. Connected between the IPC and core logic 13 of the semiconductor chip is a boundary scan circuit 12. The output of the core logic 13 is connected to a boundary scan circuit 12, which further connects the output signal to an output pad circuit (OPC) 14. The architecture of boundary scan was developed primarily to test interconnect between packaged devices and was expanded to allow testing of core logic 13. A test access port (TAP) controller 15 located on the semiconductor chip is used to control the boundary scan circuits and the shifting of data between the boundary scan circuits using a scan in 16 and scan out 17 method.
FIG. 1B demonstrates an architectural configuration where a boundary-scan cell (BC) 17 is interposed between logic blocs 18a and 18b and pad cells 16 on a chip or multiple chips as represented by logic block 1 (18a) and logic block 2 (18b). The tap controller 15 controls the operation of the boundary-scan circuits 17. The pad cells 16 are either receiving devices IPC or output devices OPC depending on the structure of the logic of the logic blocks 18a and 18b. Each pad cell 16 is connected to a BC Cell 17, which is further connected to the logic blocks 18a and 18b. 
FIG. 2A shows a boundary scan circuit 12 of prior art in which “Data In” is connected to the boundary scan circuit from an input pad circuit 10. The boundary scan circuit has two portions, a freeze circuit 20 and a transparent circuit 25. The freeze circuit 20 is used to scan test data in and out in of a shift register formed by interconnected boundary circuits and to capture data present on the “Data In” from a pad cell. A capture register CAP 22 is clocked to capture “Data In” or “Scan In” from the input register 23. The data captured by the capture register 22 is scanned out to an adjacent boundary scan circuit (scan out) and can be used to update the data in the update register (UPD) 24 under the control of an update clock. The transparent circuit 25 receives data from the “Data In” emanating from the connected pad cell and from the update register 24. A mode signal connected to G1 of the transparent circuit 21 selects either “Data In” or the output of the update register 24 to be connected to “Data Out”.
FIG. 2B shows a boundary scan circuit of prior art in which “Data Out” of the transparent circuit 21 serves as an data source for the freeze circuit 20. “Data In” connected to the Transparent circuit 21 provides a data signal from a semiconductor chip internal logic circuits and “Data Out” is connected to an output pad cell OPC (FIG. 1A). The operation of the freeze circuit 20 and the transparent circuit 21 in FIG. 2B is the same as described for FIG. 2A.
The pad cells IPC and OPC comprise input and output circuits, bidirectional circuits, and the pad cell can comprise a pull up or pull down function, latch-up protection and ESD (electrostatic discharge) circuit. During the application of a sleep mode to circuitry in a digital system, it is possible that a circuit providing “Data In” to the boundary scan device floats or is otherwise is in a voltage state that causes a leakage current to flow through the transparent circuit. The prevention of this leakage current is important to reducing power in sleep mode as well as providing stability to the computer system, thereby restricting the output signals of the boundary scan circuitry from affecting the core logic of the integrated circuit chips upon which the boundary scan circuitry is resident.